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Sheet目录3886

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SC16C850

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Product data sheet

Rev. 2 — 11 November 2010

32 of 55

NXP Semiconductors

SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software flow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

[1]

Enhanced function control bits IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].

Table 23.

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

Automatic CTS flow control.

logic 0 = automatic CTS flow control is disabled (normal default condition)

logic 1 = enable automatic CTS flow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin returns

to a logical 0.

EFR[6]

Automatic RTS flow control. Automatic RTS may be used for hardware flow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is filled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware flow

control. RTS functions normally when hardware flow control is disabled.

logic 0 = automatic RTS flow control is disabled (normal default condition)

logic 1 = enable automatic RTS flow control

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C850 compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit 0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software flow

control must be disabled (EFR[3:0] must be set to a logic 0).

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modified and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C850 enhanced

functions.

logic 0 = disable/latch enhanced features[1]. (Normal default condition.)

logic 1 = enables the enhanced functions[1].

3:0

EFR[3:0]

Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.

Combinations of software flow control can be selected by programming these

bits. See Table 24.

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